What Is ISP Pinout

ISP (In-System Programming) pinout refers to the technique of connecting a hardware programmer directly to the NAND flash storage pads on a device's PCB, bypassing the main CPU and operating system entirely. On the Samsung Galaxy A73 5G (SM-A736), the internal storage uses a UFS 2.2 interface. By identifying and probing the correct UFS test points on the A736 motherboard, technicians gain raw read/write access to the flash chip. This method is essential when normal USB-based flashing routes—such as Odin or EDL mode—are unavailable or blocked. Direct NAND access allows complete firmware dumps, partition-level edits, and security data removal without relying on the device's own boot chain.

When Technicians Use ISP

ISP access on the SM-A736 is typically a last-resort tool reserved for scenarios where conventional software methods have failed. Common situations include:

  • Hard-bricked devices that show no sign of life and do not enumerate over USB in any mode.
  • FRP (Factory Reset Protection) lock that cannot be bypassed through EDL or ADB because the bootloader rejects unauthorized commands.
  • Corrupt bootloader or modem partition causing a permanent boot loop that Odin cannot resolve.
  • Forgotten screen lock combined with FRP, where both barriers must be cleared at the storage level.
  • Dead-boot repair after a failed OTA or manual flash has left the device unresponsive.

In each of these cases, the ISP route gives the technician direct authority over the raw storage, independent of any firmware state.

SM-A736 ISP Test Points

The SM-A736 motherboard exposes UFS interface pads near the UFS package on the back side of the PCB. The relevant signal lines required for ISP programming are listed below. Due to the fine-pitch nature of UFS test pads on this board, precise location coordinates are not published here to avoid error; technicians should verify pad positions under magnification against a known PCB diagram before making contact.

  • VCCQ – 1.8 V I/O power supply for the UFS PHY layer.
  • VCC – 2.9 V core power supply for the UFS flash die.
  • GND – Common ground reference.
  • DATA Lane 0 (TX+/TX−) – Primary high-speed differential transmit pair.
  • DATA Lane 0 (RX+/RX−) – Primary high-speed differential receive pair.
  • REF CLK+/REF CLK− – Reference clock differential pair for UFS PHY synchronization.
  • RESET_N – Active-low hardware reset line to the UFS device.

Step-by-Step Access Procedure

Follow this sequence carefully to connect your programmer to the A736 test points:

  • Power down the device completely and disconnect the battery flex connector.
  • Clean the target PCB area with isopropyl alcohol (99%) and inspect pads under a stereo microscope.
  • Set your programmer (e.g., EasyJTAG Plus or UMT Pro) to UFS 2.2 mode before making any contact.
  • Solder or press fine-tipped probes to VCCQ, VCC, GND, REF CLK± and DATA Lane 0 TX±/RX± pads.
  • Connect RESET_N if your programmer requires an explicit reset sequence.
  • Power the programmer interface first, then allow it to supply the required UFS voltages—do not reconnect the battery.
  • Launch the programmer software, select Samsung SM-A736, and initiate detection before issuing any read or write command.

Safety Tips and Precautions

Working at the ISP level carries real risk of permanent data loss or PCB damage. Observe these precautions:

  • Voltage discipline: VCCQ must not exceed 1.8 V and VCC must not exceed 3.0 V. Over-voltage will destroy the UFS die instantly.
  • ESD protection: Wear an anti-static wrist strap and work on a grounded mat at all times.
  • Full backup first: Always perform a complete UFS dump and save it before attempting any write or erase operation.
  • Confirm programmer compatibility: Verify your tool explicitly supports UFS 2.2 on SM7325 platforms before connecting.
  • No battery during ISP: Running ISP with the battery connected risks uncontrolled voltage spikes that can brick the UFS permanently.

Pin / Test Point Reference

PinDescription
VCC2.9 V core power for UFS flash die — Do not exceed 3.0 V
VCCQ1.8 V I/O supply for UFS PHY layer — Do not exceed 1.8 V
GNDCommon ground reference
TX+ / TX−UFS DATA Lane 0 differential transmit pair
RX+ / RX−UFS DATA Lane 0 differential receive pair
REF CLK+ / REF CLK−Reference clock differential pair for UFS PHY
RESET_NActive-low hardware reset to UFS device

Tools required: EasyJTAG Plus (with UFS 2.2 adapter), UMT Pro Box, Medusa Pro II, Riff Box 2 (UFS module), Stereo microscope, Fine-tip soldering iron or probe clips, 99% isopropyl alcohol

Supported operations: Read Firmware / Full UFS Dump, FRP Erase, Dead Boot Repair, Partition-Level Write, Bootloader Repair, Screen Lock Removal

⚠ Safety note: UFS VCCQ max 1.8 V, VCC max 3.0 V. Disconnect battery before ISP. ESD precautions mandatory. Always dump full flash before any write operation.