What Is ISP Pinout

ISP (In-System Programming) is a hardware-level technique that allows technicians to communicate directly with the NAND flash storage on a device's PCB, bypassing the main CPU and operating system entirely. On the Samsung SM-A35 (A3560), the UFS memory chip is accessed via dedicated test pads that expose the core flash bus signals — CLK, CMD, and DAT lines — directly on the motherboard. This method enables read and write operations on the UFS storage without requiring a functional USB port, bootloader, or display. ISP is the most reliable method available when software-based tools fail to detect the device or when the device cannot boot to a recoverable state.

When To Use This Method

ISP access on the SM-A35 becomes necessary under several specific failure conditions. The most common scenarios include:

  • A damaged or non-functional USB-C port that prevents PC detection via ADB, Download Mode, or EDL.
  • A corrupted boot partition or damaged bootloader that causes a permanent boot loop or blank screen.
  • FRP (Factory Reset Protection) lock that cannot be bypassed through software or fastboot methods.
  • Failed OTA updates or interrupted firmware flashes that have left the UFS in a partially written, unbootable state.
  • Situations requiring a full raw firmware dump for backup or forensic purposes.

In all these cases, ISP provides a direct hardware pathway to the UFS chip, making recovery possible when all software routes are exhausted.

SM-A35 ISP Test Points

The SM-A35 motherboard exposes UFS bus signals through small copper test pads typically located near the UFS memory chip. The standard ISP pinout for this device is as follows:

  • CLK — UFS clock signal pad, used to synchronize data transfer.
  • CMD — Command line for sending read/write instructions to the UFS chip.
  • DAT0 — Primary data line; minimum required for basic ISP communication.
  • DAT1, DAT2, DAT3 — Additional data lines for full 4-bit bus width operation.
  • VCC — Main power supply for the UFS chip (typically 2.7V–3.6V).
  • VCCQ — I/O voltage rail for UFS signaling (typically 1.8V).
  • GND — Common ground reference.

Note: Exact PCB pad coordinates and silkscreen labels for the SM-A35 have not been independently verified. Always cross-reference with a confirmed board scan before soldering.

Step-By-Step Access Procedure

Begin by powering down the device completely and removing the back cover using a heat gun and prying tools. Disconnect the battery flex connector before proceeding. Carefully remove the motherboard shielding cans using hot air and appropriate shielding removal tools to expose the UFS chip area. Identify the ISP test pads using a verified board diagram or multimeter continuity check against known reference points. Solder thin 30AWG wire leads to each pad — CLK, CMD, DAT0–DAT3, VCC, VCCQ, and GND — taking care not to bridge adjacent pads. Connect the wires to your ISP adapter or socket, then attach it to your chosen ISP tool. Power the board externally if required and launch your ISP software to detect the UFS chip.

Safety Tips and Precautions

Always confirm supply voltage before connecting. The SM-A35 UFS chip operates on VCC at 2.7V–3.6V and VCCQ at 1.8V — exceeding these values will permanently destroy the chip. Use an ESD wrist strap and anti-static mat throughout the procedure. Never attempt ISP on a device with the battery still connected. Back up any readable data before performing erase or write operations, as these are irreversible. Use a regulated bench power supply rather than relying solely on the ISP tool's onboard power rails. Verify all solder joints are clean and isolated before powering on.

Pin / Test Point Reference

PinDescription
CLKUFS clock signal — synchronizes all data transfers between tool and UFS chip. — Exact pad location unverified; cross-reference with board scan
CMDCommand line — carries read/write command signals to the UFS controller. — Exact pad location unverified
DAT0Primary data line — minimum required pin for ISP communication. — Exact pad location unverified
DAT1Second data line for 4-bit bus width operation. — Exact pad location unverified
DAT2Third data line for 4-bit bus width operation. — Exact pad location unverified
DAT3Fourth data line for full 4-bit UFS bus. — Exact pad location unverified
VCCMain UFS power rail — typically 2.7V to 3.6V. — Verify voltage before connecting
VCCQUFS I/O voltage rail — typically 1.8V for signal levels. — Verify voltage before connecting
GNDCommon ground reference for all ISP signals.

Tools required: EasyJTAG Plus, UMT (Ultimate Multi Tool), Medusa Pro II, RIFF Box 2, UFI Box, 30AWG soldering wire, Hot air rework station, Regulated bench power supply, ESD wrist strap and mat

Supported operations: Read Firmware (Full UFS Dump), Write Firmware (Flash), FRP Erase, Dead Boot Repair, IMEI Repair, Bootloader Restore

⚠ Safety note: UFS VCC = 2.7–3.6V, VCCQ = 1.8V. Overvoltage permanently destroys the chip. Disconnect battery before work. Use ESD protection at all times. All ISP write/erase operations are irreversible — read and back up first.